GL Communications (News - Alert) Inc., a major player in providing PC-based test, analysis and simulation products and consulting services to the worldwide telecommunications industry, has announced the availability of T1 E1 ATM BERT software.

“GL’s T1 E1 ATM Bit Error Rate Test (BERT) application permits BER testing across an ATM channel operating over PDH circuits. The application transmits a BERT pattern using the simplest ATM Adaptation Layer, i.e. AAL0. The BERT pattern is inserted in its entirety into the 48 byte payload of the cell. Cells are either ‘BERT payload’ or ‘idle’ cells. Note that ‘cell headers’ and payload can overlap the framing position,” said Jagdish Vadalia, senior manager of product development for the company, in a statement.

Vadalia said that in contrast to traditional BERT, ATM BERT is done at the ATM layer and can be performed all of the way across the virtual circuit to the far-end customer-premise site.

He said that often, user traffic may be routed through several CO sites before reaching the first ATM edge switch. Each of these additional routes adds to the potential for errors. Traditional BERTs may only verify the local loop to the first CO and neglect to verify the connections between the intermediate COs. Thus ATM BERT allows for end-to-end verification of the circuit’s reliability.

“ATM BERT application allows traffic generation and verification, bit error insertion, looping back incoming traffic, and configuring ATM header fields such as virtual path and circuit identifier values, GFC, PT, and CLP for UNI & NNI interfaces,” said Vadalia.

He said that it is capable of testing Pseudo Random Bit Sequence (PRBS) patterns, fixed patterns like all ones, all zeroes, alternate ones & zeroes, 1:1, 1:7, and user-defined bit patterns. In addition, single bit error insertion rate, error insertion from 10-2 to 10-9, invert and scrambling options are provided for payload.

TMCnet in September reported that GL Communications has introduced its latest T1 E1 Hardware product feature Clock Slip Measurement, which monitors Clock and Frame Slips on T1 E1 Lines.

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